| Server IP : 46.245.81.90 / Your IP : 216.73.216.85 Web Server : Apache System : Linux server3ir.xdlhost.com 4.18.0-553.30.1.lve.el8.x86_64 #1 SMP Tue Dec 3 01:21:19 UTC 2024 x86_64 User : gmparts ( 1037) PHP Version : 8.1.34 Disable Function : exec,passthru,shell_exec,system MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : ON | Sudo : OFF | Pkexec : OFF Directory : /lib64/python3.6/multiprocessing/__pycache__/ |
Upload File : |
3 \ � @ s� d dl Z d dlZd dlZd dlZd dlZd dlZddlmZmZ ddl m Z dgZ ej dkrvd dl Z G dd� de�Zn,G d d� de�Zd d � Zd d � Zejee� G dd� de�ZG dd� de�ZdS )� N� )� reduction�assert_spawning)�util� BufferWrapperZwin32c @ s, e Zd Zej� Zdd� Zdd� Zdd� ZdS )�Arenac C sz || _ xTtd�D ]@}dtj� t| j�f }tjd||d�}tj� dkrHP |j � qW t d��|| _ || _ | j | j f| _ d S )N�d z pym-%d-%sr )�tagnamer z Cannot find name for new mmap���)�size�range�os�getpid�next�_rand�mmap�_winapiZ GetLastError�close�FileExistsError�name�buffer�_state)�selfr �ir Zbuf� r �,/usr/lib64/python3.6/multiprocessing/heap.py�__init__" s zArena.__init__c C s t | � | jS )N)r r )r r r r � __getstate__1 s zArena.__getstate__c C s, | \| _ | _| _tjd| j | jd�| _d S )Nr )r r )r r r r r )r �stater r r � __setstate__5 s zArena.__setstate__N) �__name__� __module__� __qualname__�tempfileZ_RandomNameSequencer r r r r r r r r s r c @ s e Zd Zddd�ZdS )r r c C s� || _ || _|d kr�tjdtj� tj� d�\| _}tj|� tj | tj | jf� t | jddd��^}d }||kr�d| }x t || �D ]}|j |� q�W ~|j d|| � |j� |ks�t�W d Q R X tj| j| j �| _d S ) Nr zpym-%d-)�prefix�dir�wbF)�closefdi � r i )r �fdr# Zmkstempr r r Z get_temp_dir�unlink�Finalizer �openr �write�tell�AssertionErrorr r )r r r) r �fZbsZzeros�_r r r r @ s" zArena.__init__Nr )r )r r! r" r r r r r r > s c C s( | j dkrtd��t| jtj| j �ffS )Nr zDArena is unpicklable because forking was enabled when it was createdr )r) � ValueError� rebuild_arenar r ZDupFd)�ar r r � reduce_arenaS s r5 c C s t | |j� �S )N)r �detach)r Zdupfdr r r r3 Y s r3 c @ sZ e Zd ZdZejfdd�Zedd� �Zdd� Z dd � Z d d � Z d d � Z dd� Z dd� ZdS )�Heap� c C sJ t j� | _tj� | _|| _g | _i | _i | _ i | _ t � | _ g | _ g | _d S )N)r r �_lastpid� threadingZLock�_lock�_size�_lengths� _len_to_seq�_start_to_block�_stop_to_block�set�_allocated_blocks�_arenas�_pending_free_blocks)r r r r r r f s z Heap.__init__c C s |d }| | | @ S )Nr r )�nZ alignment�maskr r r �_roundups s z Heap._roundupc C s� t j| j|�}|t| j�krj| jt| j|�tj�}| jd9 _t j d|� t |�}| j j |� |d|fS | j| }| j| }|j� }|s�| j|= | j|= |\}}}| j||f= | j||f= |S )N� z"allocating a new mmap of length %dr )�bisectZ bisect_leftr= �lenrG �maxr< r �PAGESIZEr �infor rC �appendr> �popr? r@ ) r r r �length�arena�seq�block�start�stopr r r �_mallocy s" z Heap._mallocc C s� |\}}}y| j ||f }W n tk r0 Y nX | j|�\}}y| j||f }W n tk rf Y nX | j|�\}}|||f}|| }y| j| j|� W n. tk r� |g| j|< tj| j|� Y nX || j||f< || j ||f< d S )N) r@ �KeyError�_absorbr? r> rN rI Zinsortr= ) r rS rQ rT rU Z prev_blockr1 Z next_blockrP r r r �_free� s( z Heap._freec C s^ |\}}}| j ||f= | j||f= || }| j| }|j|� |sV| j|= | jj|� ||fS )N)r? r@ r> �remover= )r rS rQ rT rU rP rR r r r rX � s z Heap._absorbc C sF x@y| j j� }W n tk r& P Y nX | jj|� | j|� qW d S )N)rD rO � IndexErrorrB rZ rY )r rS r r r �_free_pending_blocks� s zHeap._free_pending_blocksc C s` t j� | jkst�| jjd�s,| jj|� n0z"| j� | j j |� | j |� W d | jj � X d S )NF) r r r9 r/ r; �acquirerD rN r\ rB rZ rY �release)r rS r r r �free� s z Heap.freec C s� d| kot jk n s t�tj� | jkr4| j� | j�h | j� | j t |d�| j �}| j |�\}}}|| }||k r�| j |||f� |||f}| jj|� |S Q R X d S )Nr r )�sys�maxsizer/ r r r9 r r; r\ rG rK � _alignmentrV rY rB �add)r r rQ rT rU Znew_stoprS r r r �malloc� s z Heap.mallocN)r r! r" rb r rL r � staticmethodrG rV rY rX r\ r_ rd r r r r r7 b s r7 c @ s" e Zd Ze� Zdd� Zdd� ZdS )r c C sN d| kot jk n s t�tjj|�}||f| _tj| tjj |fd� d S )Nr )�args) r` ra r/ r �_heaprd r r r+ r_ )r r rS r r r r � s zBufferWrapper.__init__c C s& | j \\}}}}t|j�||| � S )N)r � memoryviewr )r rQ rT rU r r r r �create_memoryview� s z BufferWrapper.create_memoryviewN)r r! r" r7 rg r ri r r r r r � s )rI r r r` r# r: �contextr r � r �__all__�platformr �objectr r5 r3 �registerr7 r r r r r �<module> s$