HEX
Server: LiteSpeed
System: Linux server3ir.xdlhost.com 4.18.0-553.30.1.lve.el8.x86_64 #1 SMP Tue Dec 3 01:21:19 UTC 2024 x86_64
User: gmparts (1037)
PHP: 8.1.34
Disabled: NONE
Upload Files
File: //lib/firmware/qcom/shikra/lpaicp_dtb.mbn
ELF� p�44 ���  p� p��s�s�h 
x�
����|�G�0���7�e�s���]p�z��~���ZBq+����̪�s?݇^�ɾ!:,<c�ݥ'�Ӣ.'��(��j�w4D.�'4D��k�r�0e0�����_�#[�2c���}���#��(wH�}H���/H�j&��1��t3��)�N	��ߦ��K�6�ʧ��V�|ڴ5@�֌0��0�:�0
*�H�=0��10	UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U	San Diego10U
QUALCOMM10UCDMA Technologies1200U)General Use Test Key 0 (for testing only)0
260619133404Z
460614133404Z0f10	UUS10U
California10USecTools Test User10U
SecTools10U	San Diego0v0*�H�=+�"bsM�2W9�߾C�5.��S�!��B���"��]�O!��hi)��Dx�{��h&�4���њ�De�ͦ>��X������	�>��8w9y.z�o0m0U#0���w���DM2�@tXϙ�L�0	U00U�0U%0
+0Ue��
��8�J����{{�a0
*�H�=h0e1�E�-��O>�#9��5��JI�Ww���F���^'�p�R��~���ԇ0]8O����Ì+~�-M����ʀ$ܦ��y���(qX���?60��0�u�0
*�H�=0��10	UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U	San Diego10U
QUALCOMM10UCDMA Technologies100.U'General Use Test Key (for testing only)0
160321215215Z
360316215215Z0��10	UUS1,0*U#SECTOOLS SECP384R1 CURVE TEST ROOT010U	San Diego10U
QUALCOMM10UCDMA Technologies1200U)General Use Test Key 0 (for testing only)0v0*�H�=+�"b�T�}��I%���O�[�H���p����]�� f�{�I/C#�9g@�q�Kx�?jE���yAs�Ԝh�'�$,���H
pe���y�py�P5��`0^0U#0�o�q�'��s�	֟>q�b0U��w���DM2�@tXϙ�L�0U0�0U0
*�H�=i0f1�‚_H��9<�}���	ͣ�����b�:v࣮^6��+<�[��61�ft���Wzcv�ž�$��ֱ(9�	�@�n���)f��>�F�߲40��0�N�0
*�H�=0��10	UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U	San Diego10U
QUALCOMM10UCDMA Technologies100.U'General Use Test Key (for testing only)0
160321215211Z
360316215211Z0��10	UUS1+0)U"SECTOOLS SECP384R1 CURVE TEST ROOT10U	San Diego10U
QUALCOMM10UCDMA Technologies100.U'General Use Test Key (for testing only)0v0*�H�=+�"b3��x�~�
�ҩ���/פ{���Py�jh`��7_�줎��j^��K1o�$�lTg]���ء�[�SQ�q6 /�PZ����o�T:ާ�%i�1>}���`�<0:0Uo�q�'��s�	֟>q�b0U0�0U0
*�H�=h0e0u�(�C9�u���T(&�\�L<�t���Bv���ɿ�xJ��܀s6U�1�H�/�h#8o&&
����>Ga���T�׍)��,$���W�������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
��s�8b(�a�sifive,e61,shikra_lpaicp_board
&SiFive E6cpuscpu@0sifive,e66,cpu8	<rv32imacFokayMinterrupt-controllerriscv,cpu-intc^o�power-statesstate0zephyr,power-state
�runtime-idle����
�state1zephyr,power-state�suspend-to-ram���P���socsifive-socmem_port@800000008��clint@70000sifive,clint0�8interrupt-controller@80000sifive,aplic-1.0.0^o�8@@� �chkctlidc���excl_handler@20140008@ cpu_upper_plic@20100008pcpu_upper_clint@20102008`beu@20000qcom,sifive-beu8l2pfqcom,sifive-l2pfFokay",�
5:Rl2ecqcom,sifive-l2ecFokayM@]l��dtim@b4402000
sifive,dtim08�@ 0�memtimer@2001000qcom,timer83rvcp-remapper@208d000qcom,rvcp-remapper-v38���@`rvcp-remapper@208d100qcom,rvcp-remapper-v38�`��`interrupt_conditioningqcom,interrupt-conditioningFokay�����/@01rvcp_nmi_handlerqcom,rvcp-nmi-handlerFokayX�kz@������watchdogqcom,hwdog-qtmr������6�K�Ppp+>JFokayqntm_proc_configqcom,qntm-proc-configVlmcu[[LMCU]iqntm:lmcu u
qntm_apss_glink_configqcom,qntm-apss-glink-config
lmcu_uefisys_m_smsmqcom,sys_m_smsmhostqcom,sys_m_smsm-host�lpaicpendpointsqcom,sys_m_smsm-endpointsendpoint-01����master-kernel�
�slave-kernelmpmqcom,sleep-aoss-drvsleep_rpmqcom,sleep-aoss-drvglinkqcom,glink0�proc-infoqcom,glink-proc-info�xport-smem-configqcom,glink-xport-smem-configedge-01��@���N xport-rpm-configqcom,glink-xport-rpm-configD_pxport-rpm-edgesqcom,glink-xport-rpm-edgesedge-01
%rpm_0_0_0/lm2r:r2lm�smem
qcom,smemETh@0 r 0�
@
@smp2pqcom,smp2pproc-infoqcom,smp2p-proc-info�lmcu���smp2p-interruptsqcom,smp2p-interruptsintr-01�V�intr-02�V�ipc_routerqcom,ipc-routerproc-infoqcom,ipc-router-proc-info�lmcu�devcfg-glink-xals"qcom,ipc-router-devcfg-glink-xalsedge-01�SMEM�apss�IPCRTR��(� ��� �gpio-controllersqcom,gpio-controllerstlmm@40500000
qcom,tlmm8@Pp����Dz{ summarydirectconn0directconn1.�@Ppinmuxqcom,tlmm-pinmuxqup0_se0_l0\`�qup0_se0_l1\`�qup0_se0_l2\`�qup0_se0_l3\`�qup0_se1_l0\`�	qup0_se1_l1\`�
qup0_se1_l2_mira\`�
qup0_se1_l2_mirb\`�qup0_se1_l3_mira\`�qup0_se1_l3_mirb\`�qup0_se2_l0\`�qup0_se2_l1\`�qup0_se2_l2\`�qup0_se2_l3\	`�qup0_se3_l0\
`�qup0_se3_l1\`�qup0_se3_l2\`�qup0_se3_l3\
`�qup0_se4_l0\`�qup0_se4_l1\
`�qup0_se4_l2\
`�qup0_se4_l3\`�qup0_se5_l0\`�qup0_se5_l1\`�qup0_se5_l2\`�qup0_se5_l3\`�qup0_se6_l0\`�qup0_se6_l1\`� qup0_se6_l2\`�!qup0_se6_l3\`�"qup0_se7_l0\`�#qup0_se7_l1\`�$qup0_se7_l2\`�%qup0_se7_l3\`�&qup0_se8_l0\`�'qup0_se8_l1\`�(qup0_se8_l2\`�)qup0_se8_l3\`�*qup0_se9_l0_mirb\0`�+qup0_se9_l1_mirb\1`�,qup0_se9_l2_mirb\2`�-qup0_se9_l3_mirb\3`�.tlmm-pinctrl
qcom,pinctrltop_qup0_se0_i2c_activen�6top_qup0_se0_i2c_sleepn���7top_qup0_se0_spi_active n � � � ��8top_qup0_se0_spi_sleep n�9top_qup0_se0_uart_active n�����:top_qup0_se0_uart_sleep n    �;top_qup0_se1_i2c_activen	
�<top_qup0_se1_i2c_sleepn	�
��=top_qup0_se1_spi_active n	 �
 � � ��>top_qup0_se1_spi_sleep n	
�?top_qup0_se1_uart_active n	�
�
���@top_qup0_se1_uart_sleep n	 
 
  �Atop_qup0_se2_i2c_activen�Btop_qup0_se2_i2c_sleepn���Ctop_qup0_se2_spi_active n � � � ��Dtop_qup0_se2_spi_sleep n�Etop_qup0_se2_uart_active n�����Ftop_qup0_se2_uart_sleep n    �Gtop_qup0_se3_i2c_activen�Htop_qup0_se3_i2c_sleepn���Itop_qup0_se3_uart_active n�����Jtop_qup0_se3_uart_sleep n    �Ktop_qup0_se4_i2c_activen�Ltop_qup0_se4_i2c_sleepn���Mtop_qup0_se4_uart_active n�����Ntop_qup0_se4_uart_sleep n    �Otop_qup0_se5_i2c_activen�Ptop_qup0_se5_i2c_sleepn���Qtop_qup0_se5_spi_active n � � � ��Rtop_qup0_se5_spi_sleep n�Stop_qup0_se5_uart_active n�����Ttop_qup0_se5_uart_sleep n    �Utop_qup0_se6_i2c_activen �Vtop_qup0_se6_i2c_sleepn� ��Wtop_qup0_se6_spi_active n �  �! �" ��Xtop_qup0_se6_spi_sleep n !"�Ytop_qup0_se6_uart_active n� �!�"��Ztop_qup0_se6_uart_sleep n   ! " �[top_qup0_se6_i3c_activen �\top_qup0_se6_i3c_sleepn �]top_qup0_se7_i2c_activen#$�^top_qup0_se7_i2c_sleepn#�$��_top_qup0_se7_uart_active n#�$�%�&��`top_qup0_se7_uart_sleep n# $ % & �atop_qup0_se8_i2c_activen'(�btop_qup0_se8_i2c_sleepn'�(��ctop_qup0_se8_spi_active n' �( �) �* ��dtop_qup0_se8_spi_sleep n'()*�etop_qup0_se8_uart_active n'�(�)�*��ftop_qup0_se8_uart_sleep n' ( ) * �gtop_qup0_se9_i2c_activen+,�htop_qup0_se9_i2c_sleepn+�,��itop_qup0_se9_spi_active n+ �, �- �. ��jtop_qup0_se9_spi_sleep n+,-.�ktop_qup0_se9_uart_active n+�,�-�.��ltop_qup0_se9_uart_sleep n+ , - . �mtlmm_port@0qcom,gpio-portP8@� �/tlmm_port@1qcom,gpio-portP8@� �0tlmm_port@2qcom,gpio-portP8@� �1tlmm_port@3qcom,gpio-portP8@� �2tlmm_port@4qcom,gpio-portP8@� �3tlmm_port@5qcom,gpio-portP8@��4tlmm-interfaceqcom,gpio-nexusPv���������x�/ 0@1`2�3�4timetickqcom,timeticktimer@02002000qcom,timetick-timer8 �SystemTimer�$��$timer@02003000qcom,timetick-timer80�WakeUpTimer�$��%icbarbqcom,icbarbclock-controllersqcom,ccclock-controller@414000005qcom,gcc-shikraqcom,cc-shikraqcom,clock-controller8A@�GCC_CLK_CTL_REG��5regulatorsqcom,regulatorvdd_mxaqcom,rpm-regulator�/vcs/vdd_mx���%/vcs/vdd_cx/vlvl8rwcxRvlvl]vdd_cxqcom,rpm-regulator�/vcs/vdd_cx���%/vcs/vdd_mx/vlvl8rwmxRvlvl]ipcc
qcom,ipccipcc@2073000qcom,ipcc-protocol80mMPROC{����ipcc_legacy@207300080ipcc_legacy_rpmqcom,ipcc-legacy�� |}~�ipcc_legacy_appsqcom,ipcc-legacy��01� ipcc_legacy_cdspqcom,ipcc-legacy����@ipcc_legacy_mpssqcom,ipcc-legacy�����ipcc_legacy_tzqcom,ipcc-legacy��N�TOP_QUP_0@4a00000qcom,qup-v2-controller8��core2xcores-ahbm-ahb �5w5��X5�ş�5y��.��(��7A
H�\o�����FokayTOP_QUP_0_SE_0qcom,se-v2-controller��0����	2;CV^h�se-clk�5V�9�Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�6�7�8�9�:�;	FdisabledTOP_QUP_0_SE_1qcom,qup-uart�@�0����	
2;CV^�se-clkh�5)���Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�<�=�>�?�@�AFokay�-�TOP_QUP_0_SE_2qcom,se-v2-controller���0����	2;CV^h�se-clk�5S<,Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�B�C�D�E�F�G	FdisabledTOP_QUP_0_SE_3qcom,se-v2-controller���0����	2;CV^h�se-clk�5����.si2c-defaulti2c-sleepuart-defaultuart-sleep�H�I�J�K	FdisabledTOP_QUP_0_SE_4qcom,se-v2-controller��0����	2;CV^h�se-clk�5b�G.si2c-defaulti2c-sleepuart-defaultuart-sleep�L�M�N�O	FdisabledTOP_QUP_0_SE_5qcom,se-v2-controller�@�0����	
2;CV^h�se-clk�5WQ��Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�P�Q�R�S�T�U	FdisabledTOP_QUP_0_SE_6
qcom,qup-i3c���0����	2;CV^h�se-clk�5�z�Zsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleepi3c-defaulti3c-sleep�V�W�X�Y�Z�[�\�]Fokay��i3c6i3c_dev0@6A000002080070120Bqcom,qup-i3c-dev8jp�	Fdisabledbmi3x0@690000077010431000qcom,qup-i3c-dev8ipC�FokayTOP_QUP_0_SE_7
qcom,qup-i2c���0����	2;CV^h�se-clk�5i�ۯ.si2c-defaulti2c-sleepuart-defaultuart-sleep�^�_�`�aFokay	�TOP_QUP_0_SE_8qcom,se-v2-controller��0����	2;CV^h�se-clk�5

��Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�b�c�d�e�f�g	FdisabledTOP_QUP_0_SE_9qcom,se-v2-controller�@�0�	���	
2;CV^h�se-clk�5X�Dsi2c-defaulti2c-sleepspi-defaultspi-sleepuart-defaultuart-sleep�h�i�j�k�l�m	Fdisabledqup_tcsr_infoqcom,quptcsr-controller	tcsr_cfg0	'y	/>
gsi_infoqcom,gsi-controllergsi_qup_0	8�@	?>	I
	Zy;@	c	s	|3	�chosen	�/soc/dtim@b4402000&	�/soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_1swpmic-prm-stubqcom,pmic-prm-stub	�L15A_E0L17A_E0S4A_EO	�	�diag
qcom,diagdiagcfg_cmd	�	�0	�0
G
'G
AG
ZG
oG
�G
�G

�G
�GGG-G?G\GuG �G!�G#�G$�G%�G&
G'"G(4G)diagcfg_paramF�\o �������


#

A�
V
r�
��
�2
�
�
� 
�@( ?�R ax����<����3�PjK�������5Q i������ #<@Y<board-idxdefault��aliases&�/soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_1&�/soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_7&�/soc/TOP_QUP_0@4a00000/TOP_QUP_0_SE_6	#address-cells#size-cellscompatiblemodeldevice_typeregriscv,isastatuscpu-power-states#interrupt-cellsinterrupt-controllerphandlepower-state-namesubstate-idmin-residency-usexit-latency-usinterrupts-extendedreg-namesriscv,max-priorityriscv,ndevinterrupt-parentinterruptsbase-addrbasic-settingadditional-settingcache-line-sizemst-ctrlp-basecache-flush-cmd-offsetcache-flush-status-offsetcache-flush-addr-offsetmemory-regionirq-conditioning-baseplic-mask-offsetplic-type-offsetplic-clr-offsetclint-mask-offsetclint-type-offsetclint-clr-offsetexternal-interrupt-listnmi-irq-vector-regnmi-status-regnmi-cookie-regnmi-dump-pointer-regnmi-rom-patch-pre-flushnmi-rom-patch-post-flushfeed_periodbark_timebite_timeclk_freqfeed_regbark_time_regctrl_regwdt_freeze_en_maskwdt_freeze_en_shftwdt_en_maskwdt_en_shftprocproc_printsigproc_logsigproc_enumchannel_namehostremoteendpointrx_enabledrx_porttx_enabledtx_portsupported-hostsremote-hostfifo-sizemtu-sizeirq-outqos-max-ratemsg-ram-basemsg-ram-sizeremote_sstx_fifo_idrx_fifo_idsmem-this-hostsmem-version-offsettcsr-basemutex-offsets-datawonce-offsetshost-namehost-idfflagsmax-entriesdestirqtransportremote-ssch-nameoptionsstack-sizeintentsngpioswidthegpiointerrupt-namessummary-targetprocdirectconn-offsetgpio-controller#gpio-cellsmux#config-cellsconfigsgpio-map-maskgpio-map-pass-thrugpio-maptimer-nametimer-freqtimer-num#clock-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-init-microvoltqcom,resource-nameqcom,remote-resource-nameqcom,unitsqcom,lpr-enableprotocol-nameprotocol-idxworker-typeworker-prioritynum-signalsclient-mappingqcom,offsetqcom,clientqcom,out-maskclock-namesclocksqup_idqup_common_offsetse_wrapper_base_offsetcore_frequencyqup_flagsnum_seicb_master_qup_coreicb_slave_qup_coreicb_qup_ddr_mastericb_qup_ddr_slaveicb_cpu_master_procicb_cpu_qup_slavecore_offsetse_flagsse_indexFIFO_MODEprotocol_supportedinterface_supportedgpii_listnum_gpiisring_size_multipliercore_irqpdc_irqparent_wakeup_gpioi2c_hubshared_sedfs_enablepinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5current-speedpinctrl-6pinctrl-7supported_hdrlabelassigned-addressauto-suspend-delay-msnum_top_qupsirq_numqup0_cfggsi_patcsr_addrtcsr_gpii_offsettcsr_irqgpii_interruptsnum_gpiiactiveis_common_irqzephyr,sramzephyr,consoleregulatorsxob-clockcxo-stubdiag_cmd_request_fdiag_dcm_cmd_reg_test_basediag_ulogdiag_processor_iddiag_subsys_id_basediag_stress_test_loopbackdiag_start_stress_test_fdiag_get_cmd_reg_tbldiag_legacy_health_count_basediag_get_max_req_pkt_lendiag_delay_health_count_basediag_flow_control_count_basediag_subsys_mask_retrieval_basediag_f3_trace_set_configdiag_tx_mode_configdiag_get_time_apidiag_stress_test_delayed_rspdiag_uimage_health_statsdiag_start_stress_test_adv_fdiag_health_stats_basediag_get_set_drain_paramdiag_set_drain_propdiag_health_report_configdiag_get_set_client_settingsdiag_lock_buffer_apidiag_query_enablediag_get_drop_perdiag_instance_id_basediag_err_ulog_sizediag_debug_ulog_sizediag_cmd_ulog_sizediag_data_ulog_sizediag_qdss_ulog_sizediag_ctrl_ulog_sizediag_listener_ulog_sizediag_mpd_drain_timer_lendiag_mpd_buf_commit_thresh_perdiag_mpd_buf_drain_thresh_perdiag_event_timer_lendiag_event_rpt_pkt_len_sizediag_event_rpt_pkt_sizediag_drain_timer_lendiag_event_send_maxdiag_event_heap_sizediag_ctrl_send_buf_sizediag_ctrl_read_buf_sizediag_cmd_read_buf_sizediag_event_sec_heap_sizediag_dci_read_buf_sizediag_rsp_heap_sizediag_heap_sizediag_f3_trace_buf_sizediag_buf_sizediag_rsp_alloc_retry_timer_lendiag_mask_notify_timer_lendiag_tx_sleep_threshold_defaultdiag_tx_sleep_time_defaultdiag_core_pd_drain_thresholddiag_sio_timeout_timer_lendiag_cmd_read_tout_timer_lendiag_max_active_listenersdiag_many_drain_per_markdiag_few_drain_per_markdiag_hdlc_pad_lendiag_stress_task_sleep_completediag_buf_commit_thresholddiag_buffer_default_lock_statediag_deferrable_timerdiag_deferrable_timer_exdiag_send_data_buf_size_maxdiag_min_send_data_sizediag_msg_fmt_str_arg_sizediag_event_rpt_pkt_len_size_nrtdiag_event_rpt_pkt_size_nrtdiag_event_send_max_nrtdiag_event_timer_len_nrtdiag_tx_sleep_threshold_nrtdiag_tx_sleep_time_nrtdiag_drain_timer_len_nrtdiagbuf_commit_threshold_nrtdiag_mpd_commit_thresh_nrt_perproc-namechip-infouart1i2c7i3c6